How to map a port in VHDL? -

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i want build full adder in vhdl , read result 1 of pins.

entity main port (foo: out std_logic); end entity main;

given code, how map foo real pin on fpga?

here details of fpga i'm using:

  • manufacturer: xilinx
  • family: spartan 3e
  • device: xc3s500e
  • package:ft256

in xilinx ise, add file project; should automatically set top level entity. in 'processes' panel (typically near bottom left), expand 'user constraints' , double click 'i/o pin planning (planahead) - pre-synthesis'. opens planahead pin planning tool. using this, can drag port onto pin of device. saving in program should create 'constraints' (.ucf) file. can edit file manually. ise use constraints file when compiling fpga.


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