xilinx ise - Cycle delay in Verilog -

i have been struck @ point quite time , me out if can , solve it. there 4 inputs system - w, a,b,c. periodic inputs changing time. output o. stored signed 16 bit registers. when w less 16'b0000101100110011, output (o) directly equal 'a'. when w greater this, output changes 'b' happens during 0 crossing of c, i.e. when goes positive negative or vice-versa. if w greater above specified value c has not crossed 0 crossing, output 'o' continue 'a'. trying see value of msb of 'c'. changes value, trying change output 'a' 'b' not happening per given code:

module trial(clk, w, a, b, c, o     );  input clk;     input signed [15:0] w;     input signed [15:0] a;     input signed [15:0] b;     input signed [15:0] c;     output signed [15:0] o;     reg signed [15:0] temp;     reg signed [15:0] temp1;     reg signed [15:0] temp2;       @(posedge clk)      begin       if (w<16'b0000101100110011)        begin         temp = a;        end       else        begin         temp1 = 0;//initializing value of temp1         temp2 = 0;//initializing value of temp2           while (temp1 == temp2)          begin           temp1 = c[15];// storing sign bit of input 'c'           repeat(1) @(posedge clock);// 1 clock cycle delay command (##1    not working)           temp2 = c[15];//storing sign bit of input 'c' after 1 clock cycle          end         temp = b;        end       end      assign o = temp;     endmodule   

the output changes 'a' 'b' instantly when 'w' becomes greater 16'b0000101100110011. not wait fo 0 crossing of 'c'. can 1 point out if there mistake , solution. thanks

i think work too

module sample(clk, w, a, b, c, o );  input clk;     input signed [15:0] w;     input signed [15:0] a;     input signed [15:0] b;     input signed [15:0] c;     output reg signed [15:0] o;     reg signed [15:0] temp;     reg signed [15:0] temp1;     reg signed [15:0] temp2;      reg signed [15:0] c_previous; wire signed c_zero_cross;  assign c_zero_cross = (c_previous[15] == c[15]) ? 1'b0 : 1'b1;  @(posedge clk) begin      c_previous <= c;      if (w < 16'b0000101100110011) begin              o <= a;               end         else begin             if(c_zero_cross) begin             o <= b;         end else begin             o <= a;         end     end end      endmodule