system verilog - RNG state not getting preserved while using get_randstate and set_randstate -

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i'm trying understand why in following example, rng state not getting preserved:

module test;   string seed_s = "0";   int unsigned seed_i = 0;    initial   begin     process p;     p = process::self();     $display("process randstate1 = ", p.get_randstate());     seed_s = p.get_randstate();     $display("process seed_s = %s", seed_s);     seed_i = seed_s.atobin();     $display("process seed_s = %s", seed_s);     $display("process randstate2 = %d", seed_i);     p.set_randstate(seed_s);     $display("process randstate3 = ", p.get_randstate());   end endmodule

here's output:

process randstate1 = 0000000000000000000000000000000000001001011001101001101001011110 process randstate2 =  157719134 process randstate3 = 0x1z00zzxzx011z00x0zx01xzxz0x111xzzxzzzxzxzxzzxzzzzxzzzzxxxxxxxx

i expected see randstate1 = randstate3. missing here?

edit: added display string before , after atobin()

process randstate1 = 0000000000000000000000000000000000001001011001101001101001011110 process seed_s = 0000000000000000000000000000000000001001011001101001101001011110 process seed_s = 0000000000000000000000000000000000001001011001101001101001011110 process randstate2 =  157719134 process randstate3 = 0x1z00zzxzx011z00x0zx01xzxz0x111xzzxzzzxzxzxzzxzzzzxzzzzxxxxxxxx

this looks simulator bug. simulator use?

when create simplified version of code, , run cadence incisive simulator, same state before , after set_randstate:

module tb;  string seed_s;  initial begin     process p;     p = process::self();     $display("process randstate = ", p.get_randstate());     seed_s = p.get_randstate();     p.set_randstate(seed_s);     $display("process randstate = ", p.get_randstate()); end  endmodule  /*  output:  process randstate = svseed=1 ; 3130931317 ;  process randstate = svseed=1 ; 3130931317 ;   */

when run using synopsys vcs, similar results yours.


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