vhdl - D flip flop with a feedback loop to clear -

here code d flip flop active low asynchronous clear , reset. clear has input combination of q (output of d ff) , reset signal.i have uploaded image show circuit have written program. not expected output; clear , q low. have set reset logic 1 in simulation. please , let me know mistake :) thank you.

library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all;   entity d_feedback_clr port (         clock, reset, d: in std_logic ;          q : out std_logic       ) ;  end d_feedback_clr ;  architecture behavior of d_feedback_clr signal state, clear: std_logic:='0'; -- state implies output of d register  begin      clear <= reset nand state;       process (clock, clear, reset)         begin               if (clear='0')                 state <= '0';              elsif reset='0'                 state <= '1';               elsif (clock'event , clock='1')                 state <= d;                                                   end if ;      end process ;     q <= state; end behavior ; 

i think problem in clear signal. if state '1' , reset '1' clear signal, output of nand gate of these two, become '0' , state change '0'. state , q low.

i've used modelsim altera simulate design, , showed glitches in signal.